A Single Scalar DSP based Programmable H.264 Decoder

This paper presents a feasibility study of applying a legacy reconfigurable single scalar DSP processor to media processing. The latest video compression standard H.264 was adopted as target application. First, a pure software H.264 decoder was implemented based on the legacy DSP processor. Although real-time performance was not achieved, it exposed essential computational as well memory access costs. The second design explored the possibility of achieving both programmability and real-time performance with affordable hardware acceleration. At the same time, features of H.264 processing were analyzed for more suitable accelerator design. In order to avoid conflicts in memory access, tasks scheduling was carefully considered. In the end, performance of proposed solution and the bottlenecks which still limit the performance are presented as conclusion.